PCI-SIG, the organization that oversees the PCI Express I/O interconnect, has unveiled draft specification version 0.7 for the upcoming PCI-Express 7.0 standard (also known as PCIe Gen 7). The release of this draft in early 2025 suggests that PCIe Gen 7 may be finalized into specification version 1.0 by the end of the same year. This will allow implementers to use it as a basis for designing their devices.
Currently, PCIe Gen 5 offers speeds of 32 Gbps per lane in each direction. With PCIe Gen 6 doubling that to 64 Gbps, it is expected that PCIe Gen 7 will further double the speed to 128 Gbps per lane per direction. This means that a PCIe 7.0 x1 connection would provide the same bandwidth as a PCIe 3.0 x16 connection.
It is anticipated that the first computing platforms utilizing PCIe Gen 7 will be available around 2027 or possibly 2028. PCIe serves as the physical layer for various related standards, including CXL, Thunderbolt, USB (from USB 3.0 onwards), NVMe, SDexpress, CFexpress, and DMI.
Special thanks to Tumble George for the information.
