Panmnesia Unveils Industry-First PCIe 6.0/CXL 3.2 Fabric Switch with Port-Based Routing

Panmnesia, a leader in advanced AI infrastructure connectivity, has announced the sample availability of its groundbreaking PCIe 6.0/CXL 3.2 Fabric Switch. This innovative switch is the first in the industry to feature port-based routing (PBR) in CXL switch silicon, marking a significant advancement in composable data center architecture. Early access partners are now receiving samples of the new switch silicon for evaluation and integration.

Hybrid Support for PCIe Gen 6 and CXL 3.2

The Panmnesia Fabric Switch is engineered as a hybrid solution, supporting both PCIe Gen 6 and CXL 3.2 protocols on a single chip. It maintains full backward compatibility with all previous generations of PCIe and CXL, ensuring seamless interoperability and future-proofing for evolving data center needs. The switch is fully compliant with the latest CXL 3.2 and PCIe 6.0 specifications, guaranteeing robust standards adherence and reliable operation across all supported subprotocols.

Flexible Routing and Composable Architecture

Designed for maximum flexibility, the switch operates in both port-based routing (PBR) and hierarchy-based routing (HBR) modes. This versatility, combined with a full-stack optimized architecture powered by Panmnesia’s proprietary PCIe/CXL controller, enables a truly composable infrastructure. Organizations can reduce capital and operational expenditures (CAPEX/OPEX) while achieving high performance for demanding, large-scale workloads. The switch is particularly well-suited for AI applications—including deep learning recommendation models (DLRM), large language models (LLMs), and retrieval-augmented generation (RAG)—as well as high-performance computing (HPC) workloads such as MPI-based scientific simulations.

Key Features of Panmnesia’s PCIe/CXL Fabric Switch

  • Unified Fabric with Zero Manual Configuration: The switch’s PBR support enables a self-organizing, topology-agnostic fabric. Devices can be connected anywhere in the network, allowing AI clusters to function as a single, unified accelerator without the need for manual setup or static hierarchy.
  • Scalable, Low-Latency Expansion: Panmnesia’s cascading technology allows thousands of devices to be interconnected across multiple racks, eliminating the bottlenecks of traditional slow networks and minimizing latency.
  • Accelerated Data Transfers and Cache Coherency: With PCIe Gen 6 data rates of 64 GT/s, the switch accelerates bulk data movement. Full support for CXL.cache, CXL.mem, and CXL.io ensures cache coherency across devices, reducing redundant data copies and improving efficiency.
  • Ultra-Low-Latency Data Access: The high-fan-out architecture and Panmnesia’s proprietary CXL controller deliver double-digit nanosecond latency, minimizing data-access delays within clusters and supporting real-time AI and HPC workloads.

Availability and Integration

Panmnesia’s PCIe 6.0/CXL 3.2 Fabric Switch silicon is now available for early access partners. The integrated PCIe 6.0/CXL 3.2 controllers are silicon-proven and can be provided as standalone products tailored for memory, accelerator, or CPU applications. This flexibility allows data center architects and AI infrastructure providers to build scalable, high-performance systems optimized for next-generation workloads.