First Look at Huawei Ascend 950 AI Accelerator: Custom Silicon and HBM Memory
Huawei has unveiled its next-generation Ascend 950 AI accelerator, offering a glimpse into the company’s latest advancements in custom silicon and high-bandwidth memory (HBM) technology. This new AI chip marks a significant milestone for Huawei, as it integrates the company’s first self-developed HBM memory with a new generation of AI acceleration capabilities.
Ascend 950 Family: Two Powerful Variants
The Ascend 950 family is scheduled for release in early 2026 and will be available in two variants. The 950PR model features 128 GB of in-house HBM, delivering approximately 1.6 TB/s of memory bandwidth. The 950DT model takes it a step further, increasing memory capacity to 144 GB and boosting bandwidth to nearly 4 TB/s. Both models are engineered to achieve one PetaFLOP of FP8 performance and two PetaFLOPS of FP4, positioning them as strong contenders in the AI accelerator market.
System-Scale AI Performance and Competitive Strategy
While Huawei’s Ascend 950 may not yet match NVIDIA’s per-chip performance, the company is focusing on system-scale solutions to remain competitive. Huawei’s strategy centers on dense packaging and advanced networking, enabling large-scale deployments that can rival industry leaders in aggregate performance. This approach leverages the strengths of interconnected systems rather than relying solely on the raw power of individual chips.
Advanced Manufacturing with SMIC’s 5 nm Node
Although specific details about the manufacturing process have not been disclosed, it is highly likely that the Ascend 950 is produced using SMIC’s latest N+3 node, which features 5 nm-class technology. SMIC, China’s leading semiconductor foundry, has achieved volume production of its 5 nm node using deep ultraviolet (DUV) lithography. Given that Huawei’s Kirin 9030 SoC was the first product on this node, it is logical that the Ascend 950 AI accelerator would utilize the same advanced manufacturing process.
Innovative Multi-Chip Module Design
A close examination of the Ascend 950 reveals a sophisticated multi-chip module architecture. The design incorporates two main dies, along with two additional silicon dies that likely serve as I/O and networking modules. These components are essential for connecting the accelerator to Huawei’s large-scale SuperPoDs and SuperClusters, which are built from these modules. The system is interconnected using Huawei’s new Lingqu interconnect protocol and optical links, enabling the connection of hundreds of thousands of Ascend 950 cards for massive AI workloads.
Homegrown HBM Memory Integration
Surrounding the main silicon is what appears to be a hybrid of LPDDR and HBM memory, most likely representing Huawei’s proprietary HBM technology. The company is expected to package these HBM modules as standalone chips, stacking them across the package to maximize memory bandwidth and efficiency. This integration of custom HBM memory is a key differentiator for the Ascend 950, enhancing its ability to handle demanding AI applications.
With the introduction of the Ascend 950 AI accelerator, Huawei is demonstrating its commitment to advancing AI hardware through innovation in custom silicon, memory technology, and large-scale system integration. As the company prepares for the official launch in 2026, the Ascend 950 is poised to play a significant role in the evolving landscape of AI acceleration.
