AMD Begins Production of Next-Generation EPYC "Venice" Processors on TSMC 2nm Technology
AMD has announced a significant milestone in its data center CPU roadmap with the commencement of production for its next-generation EPYC processor, codenamed "Venice." Manufactured in Taiwan using TSMC’s advanced 2 nanometer (2nm) process technology, "Venice" is the first high-performance computing (HPC) product in the industry to enter production at this cutting-edge node. AMD also revealed plans to expand production to TSMC’s Arizona fabrication facility in the future, further strengthening its global manufacturing capabilities.
Driving Leadership in AI and Data Center Infrastructure
The launch of "Venice" on TSMC’s 2nm process marks a pivotal step in advancing next-generation AI, cloud, and enterprise infrastructure. As artificial intelligence adoption accelerates and workloads become increasingly complex, the role of the CPU in orchestrating data movement, networking, storage, security, and system management across the data center is more critical than ever. AMD’s EPYC processors are designed to meet these evolving demands, delivering the performance and energy efficiency required for modern cloud, enterprise, HPC, and AI deployments.
Dr. Lisa Su, Chair and CEO of AMD, emphasized the importance of this achievement, stating, “Ramping 'Venice' on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment.”
Expanding Advanced Manufacturing Footprint
Dr. C.C. Wei, Chairman and CEO of TSMC, commented, “Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing.”
Future Roadmap: Introducing "Verano" and Advanced Packaging
Looking ahead, AMD plans to extend TSMC’s 2nm process technology across its data center CPU roadmap with the introduction of "Verano," the 6th Generation EPYC processor. "Verano" is engineered for performance-per-dollar-per-watt leadership and is optimized for cloud and AI computing workloads. It will incorporate advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth, and efficiency required for power-constrained applications.
The AMD and TSMC partnership also encompasses advanced packaging technologies such as TSMC’s SoIC-X and CoWoS-L, which are integral to AMD’s broader AI and data center portfolio. By leveraging TSMC’s process and packaging expertise, AMD continues to deliver highly integrated compute platforms that address the needs of modern data centers and AI infrastructure at scale.
